| 41. | Giorgi, Roberto: Transactional Memory on a Dataflow Architecture for Accelerating Haskell. In: WSEAS Transactions on Computers, 14 , pp. 546-558, 2015, ISSN: 1109-2750. (Type: Journal Article | Abstract | Links | BibTeX) @article{Giorgi15c.bib, title = {Transactional Memory on a Dataflow Architecture for Accelerating Haskell}, author = {Roberto Giorgi}, url = {http://www.wseas.org/multimedia/journals/computers/2015/b085805-099.pdf}, issn = {1109-2750}, year = {2015}, date = {2015-02-22}, journal = {WSEAS Transactions on Computers}, volume = {14}, pages = {546-558}, abstract = {Dataflow Architectures have been explored extensively in the past and are now re-evaluated from a different perspective as they can provide a viable solution to efficiently exploit multi/many core chips. Indeed, the dataflow paradigm provides an elegant solution to distribute the computations on the available cores by starting computations based on the availability of their input data. In this paper, we refer to the DTA (Decoupled Threaded Architecture) \textendash which relies on a dataflow execution model \textendash to show how Haskell could benefit from an architecture that matches the functional nature of that language. A compilation toolchain based on the so called External Core \textendash an intermediate representation used by Haskell \textendash has been implemented for most common data types and operations and in particular to support concurrent paradigms (e.g. MVars, ForkIO) and Transactional Memory (TM). We performed initial experiments to understand the efficiency of our code both against hand-coded DTA programs and against GHC generated code for the x86 architecture. Moreover we analyzed the performance of a simple shared-counter benchmark that is using TM in Haskell in both DTA and x86. The results of these experiments clearly show a great potential for accelerating Haskell: for example the number of dynamically executed instructions can be more than one order of magnitude lower in case of Haskell+DTA compared to x86. Also the number of memory accesses is drastically reduced in DTA.}, keywords = {}, pubstate = {published}, tppubtype = {article} } Dataflow Architectures have been explored extensively in the past and are now re-evaluated from a different perspective as they can provide a viable solution to efficiently exploit multi/many core chips. Indeed, the dataflow paradigm provides an elegant solution to distribute the computations on the available cores by starting computations based on the availability of their input data. In this paper, we refer to the DTA (Decoupled Threaded Architecture) – which relies on a dataflow execution model – to show how Haskell could benefit from an architecture that matches the functional nature of that language. A compilation toolchain based on the so called External Core – an intermediate representation used by Haskell – has been implemented for most common data types and operations and in particular to support concurrent paradigms (e.g. MVars, ForkIO) and Transactional Memory (TM). We performed initial experiments to understand the efficiency of our code both against hand-coded DTA programs and against GHC generated code for the x86 architecture. Moreover we analyzed the performance of a simple shared-counter benchmark that is using TM in Haskell in both DTA and x86. The results of these experiments clearly show a great potential for accelerating Haskell: for example the number of dynamically executed instructions can be more than one order of magnitude lower in case of Haskell+DTA compared to x86. Also the number of memory accesses is drastically reduced in DTA. |
| 42. | Giorgi, Roberto: Accelerating Haskell on a Dataflow Architecture: a case study including Transactional Memory. In: Proc. Int.l Conf. on Computer Engineering and Applications (CEA), pp. 91–100, Dubai, UAE, 2015, ISBN: 978-1-61804-276-7. (Type: Inproceedings | Abstract | Links | BibTeX) @inproceedings{Giorgi15b.bib, title = {Accelerating Haskell on a Dataflow Architecture: a case study including Transactional Memory}, author = {Roberto Giorgi}, url = {http://www.wseas.us/e-library/conferences/2015/Dubai/CEA/CEA-12.pdf}, isbn = {978-1-61804-276-7}, year = {2015}, date = {2015-02-22}, booktitle = {Proc. Int.l Conf. on Computer Engineering and Applications (CEA)}, pages = {91--100}, address = {Dubai, UAE}, abstract = {A possible direction for exploiting the computational power of multi/many core chips is to rely on a massive usage of Thread Level Parallelism (TLP). We focus on the Decoupled Threaded Architecture, a hybrid dataflow architecture which efficiently uses TLP by decoupling and scheduling threads on chip processing elements in order to provide on-chip scalable performance. The DTA architecture currently lacks a specific mapping to high level languages. Our idea is to use a functional language to match this execution paradigm because we think it is very fit for this environment. We choose Haskell as our language and in particular one of the features we want to implement is the concurrency control based on Transactional Memory, which is fully supported in Haskell. The main goal of this research is twofold. First, the study of a method to unite the functional paradigm of the Haskell programming language with the DTA execution paradigm. Second, the development of a Transactional Memory model for DTA architecture based on the STM (Software Transactional Memory) API. To achieve this goals, we have implemented a tool chain, which translates simple programs from Haskell to DTA and created a first version of the Transactional Memory mechanism in DTA. Our results show promising speedup of the Haskell based front-end for the DTA architecture.}, keywords = {}, pubstate = {published}, tppubtype = {inproceedings} } A possible direction for exploiting the computational power of multi/many core chips is to rely on a massive usage of Thread Level Parallelism (TLP). We focus on the Decoupled Threaded Architecture, a hybrid dataflow architecture which efficiently uses TLP by decoupling and scheduling threads on chip processing elements in order to provide on-chip scalable performance. The DTA architecture currently lacks a specific mapping to high level languages. Our idea is to use a functional language to match this execution paradigm because we think it is very fit for this environment. We choose Haskell as our language and in particular one of the features we want to implement is the concurrency control based on Transactional Memory, which is fully supported in Haskell. The main goal of this research is twofold. First, the study of a method to unite the functional paradigm of the Haskell programming language with the DTA execution paradigm. Second, the development of a Transactional Memory model for DTA architecture based on the STM (Software Transactional Memory) API. To achieve this goals, we have implemented a tool chain, which translates simple programs from Haskell to DTA and created a first version of the Transactional Memory mechanism in DTA. Our results show promising speedup of the Haskell based front-end for the DTA architecture. |
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